Invited Speakers

Dr. Alok Ranjan

Invited Talk Topic: Dielectric Reliability Studies on Single Crystal Hexagonal Boron Nitride using Conduction AFM

Graphene and emerging 2D layered semiconductor materials have gathered enormous research interest for wide range of novel applications including optoelectronics and flexible nanoelectronics. These ultra-thin 2D semiconductor materials are highly sought after as a channel material in flexible transistors, given its intrinsic carrier mobilities are higher than silicon. While a lot of efforts have been directed towards growth of these materials on wafer scale, recent findings have shown that conventional dielectrics (e.g., SiO₂, HfO₂) are not compatible with 2D layered semiconductors. 2D hexagonal boron nitride (h-BN) have emerged as a potential dielectric material which can seamlessly integrate with almost all the 2D semiconductor materials reported so far. Hence, the reliability of h-BN as a gate dielectric is crucial for its successful commercialization. Interestingly, conduction AFM (CAFM) has been very successful to measure localized electrical properties of gate dielectrics and emerging nanoscale devices. In this talk, I will present our recent works where we extensively use CAFM to probe the electrical defects and understand mechanisms of dielectric breakdown in h-BN.

Bio: Dr. Alok Ranjan is currently a postdoctoral fellow at Engineering Product Development pillar at Singapore University of Technology and Design. Alok is passionate about developing experimental techniques for the physical and failure analysis techniques for the nanoscale devices. Alok has obtained his PhD in the field of nanoscale reliability of gate dielectrics under the mentorship of Prof. Pey Kin Leong (SUTD) and Dr. Sean O’Shea (IMRE, A*STAR). During PhD, Alok has been extensively applying the scanning probe microscopy techniques for single defect spectroscopy on gate dielectrics. Alok has published more than 20 technical papers and a book chapter, including 5+ technical papers presented as a lead author at International Reliability Physics Symposium (IRPS). Alok also sits on the reviewer panel for various journals including Applied Physics Letters, Scientific Reports, ACS Applied Materials and Interfaces, Microelectronics Reliability and conferences including International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

Dr. Francesco Puglisi

Invited Talk Topic: Random Telegraph Noise for True Random Number Generation (TRNG) Applications

Dr. Franco Stellari

Invited Talk Topic: Tool automation and computer vision methodologies for faster IC diagnostics

Automated data acquisition and analysis using scripting and Computer Vision (CV) allow one to perform repetitive tasks faster with higher accuracy. In this paper, we discuss techniques to automate analytical tools and several examples of advanced image processing and data analysis to provide accurate IC diagnostics.

Bio: Franco Stellari (S’95–M’04-SM’06) received the M.S. degree (summa cum laude) and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 1998 and 2002 respectively. He subsequently joined the IBM T.J. Watson Research Center in Yorktown Heights, NY as a post-doc, becoming a permanent Research Staff Member in 2004. His major interest is the development and use of new optical techniques for testing VLSI circuits based on static imaging, time resolved emission and laser based techniques. During the years he has worked with single-photon detectors with fast response time and very high quantum efficiency, such as InGaAs Single Photon Avalanche Diodes (SPADs) and Superconducting Single Photon Detectors (SSPD), pushing their limits towards record low voltage applications. In 1999 he developed a model of the transistor emission that is still currently used for estimating luminescence from electric circuits. He has also developed a novel methodology for studying latch-up ignition, process variability, power supply noise measurement, and signal integrity. More recently, he has worked on fully exploiting the Light Emission from Off-State Leakage Current (LEOSLC) to developed novel techniques for VLSI circuit testing and hardware security such as chip alterations detection, and logic state mapping, chip reverse engineering, etc. His work leverages the development of automated data collection, advanced analysis, image processing, and computer vision for signal isolation and data extraction. He has more than 100 international publications, more than 45 granted patents. Some of his work in the field of advanced detectors was recognized with the Paul F. Forman Team Engineering Excellence Award in 2015. He was also the recipient of the IEEE EDS Paul Rappaport Award for the best Trans. on Electron Devices of 2004, the Best Poster Award at the International Symposium for Test and Failure Analysis (ISTFA) in 2014, and the Best Paper Award at the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) twice, in 2002 and 2004.

Dr. I-Ting Wang

Invited Talk Topic: Evaluation of Breakdown Interference and Strategy of Mitigating Yield Loss in Crossbar Memory Arrays

Resistive switching memory (RRAM) is regarded as one of the promising candidates for neuromorphic computing. The realization of crossbar memory array not only accelerates ultra-high density nonvolatile data storage but also enables vector-matrix multiplication, which has opened up compute-in-memory paradigm. However, sneak current flowing from the unselected cells results in cell-to-cell interference and degrades the array sensing margin. Adding selection devices or developing self-selected memories are therefore important. Nevertheless, the interference issue may be even worse when breakdown cells exist. In this talk, I will present the simplified rule-based model, which provides a solid foundation for investigating the cell-to-cell interference due to the breakdown cells in crossbar arrays. In order to mitigate breakdown interference and array yield loss, I will introduce our latest studies and provide efficient method for ruling out defective arrays.

Bio: Dr. Wang received her Ph.D. degree in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan in 2018. She joined the Institute of Microelectronics (IME), A*STAR, Singapore, as a research scientist from 2018 to 2020. She is currently a postdoctoral researcher with the Institute of Electronics, National Yang Ming Chiao Tung University (NYCU), Hsinchu, Taiwan. Her research interests include memristors for neuromorphic computing applications and the 3D high-density emerging memory technology.

Dr. Markus Herklotz

Invited Talk Topic: BEOL Reliability Challenges using advanced nodes for automotive applications

Accompanied by the march of the automotive industry toward electrical vehicles and autonomous driving, the number of semiconductor devices per car is continuously growing. With respect to reliability an increased number of devices per vehicle, consequently, strengthen the requirements for cumulative failure rate on both intrinsic and extrinsic level. Furthermore, reliability qualification targets for ATV EEMs (electrical/electronical module) strongly depend on customer and application specific mission profiles, which reflect the time dependency of stressors like voltage, current or temperature. This talk focuses on reliability in highly integrated metallization layers (copper and aluminium) of advanced nodes and exposes the challenges for semiconductor foundries to qualify and monitor a highly ATV conformal reliable production process. Beside an overview of intrinsic and extrinsic degradation mechanisms, insights into mission profile analysis and defectivity models are provided. Qualification and monitoring strategies are illuminated and finally the required close cooperation approach with the OEM is underlined.

Bio: Dr. Markus Herklotz technically leads the Back End of Line Reliability Team at GlobalFoundries Dresden with focus on the degradation mechanisms Electromigration (EM), Time Dependent Dielectrical Breakdown (TDDB) and Stress Migration (SM) within copper and aluminum metallization of advanced nodes; furthermore, he is responsible for test structure design / validation and technology qualification and act as Reliability stakeholder in Material Review and Process Change Processes. Before Globalfoundries, he worked at Qimonda Dresden as failure analysis engineer, was responsible for Focused Ion Beam microscopy and maskless redesign (circuit edit). His professional career started at Infineon Dresden in 2002, where he gained process expertise as a shift sustaining technician in several modules, such as lithography. He received his PhD in material science in 2013, his diploma and skilled worker level in microtechnology in 2007 and 2005 respectively. Dr. Herklotz authored/co-authored more than 15 publications and holds several patents in material science with focus on structural fatigue mechanisms.

Dr. Stephen Voldman

Invited Talk Topic: Latchup: From the beginning to today

Latchup became an issue with the introduction of CMOS technology. In the beginning, latchup was a problem in space application even before CMOS was mainstream in technology and foundries. With the introduction of CMOS into mainstream technologies, and foundries, significant amount of work was required in understanding of the physics, to establishing latchup ground rules, latchup design practices, design manuals, test site structures, latchup benchmarking, to latchup testing, verification and release. Technology processes and isolation structures were also required to evolve to satisfy the needs of technology scaling. Well technology migrated from single diffused well to implanted retrograde well structures to reduce the gain of the parasitic bipolar transistors. Migration continued from single well, dual well to triple well processes. Isolation evolved from recessed oxide (ROX), LOCOS, to shallow trench evolution for scaling and improved device characteristics.With scaling, and system on chip (SOC), new latchup issues occurred. New failure types occurred, such as I/O to I/O, I/O to core, and core-to-core with integration of digital and analog cores in a common chip. In this invited talk, these latchup issues will be reviewed highlighting the elements required for successful design in advanced CMOS applications.

Bio: Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” Voldman was a member of the semiconductor development of IBM for 25 years. He also worked at Intersil, Qimonda, TSMC, and Samsung. He initiated a lecture series that reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, Senegal, Zimbabwe, and China. Dr. Voldman has teaches short courses and tutorials on ESD, latchup, patenting, and invention. He is a recipient of 264 issued US patents and has written over 150 technical papers in the area of ESD and CMOS latchup. He is an author of over 10 books on ESD, EOS and latchup. Since 2007, he has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation.

Dr. YuanYuan Shi

Invited Talk Topic: Engineering Wafer-Scale Epitaxial Transistion Metal Dichalcogenide Monolayer for Advanced High-Performance Nanoelectronic Devices

Abundant-data computing such as big-data analytics, artificial intelligence (AI) and Internet of Things (IoT) demand extreme energy efficiency and concomitant improvement of cost performance of the electronic systems. Field-effect transistors (FETs) represent the fundamental building blocks for modern computer processors. The number of transistors in a typical microprocessor has followed a remarkable exponential growth since the 1960s, a trend known as Moore’s law. By making the device smaller, more transistors can be packed into a single chip with much improved performance and reduced cost. The continued miniaturization of silicon microelectronics has fuelled the exponential growth of the integrated circuits for over half a century. Today, as silicon transistors enter the sub-10nm technology node with increasing technical challenges, the exploration of alternative device geometries or new channel materials is ever more important for future processor chip. Atomically thin two-dimensional (2D) semiconductors have attracted tremendous interest as a new channel material that could facilitate continued transistor scaling. To benefit from continuous scaling, the performance of the scaled 2D transistors needs to outperform Si technology nowadays. However, significant efforts are still required for channel material deposition, gate stack development, contact resistance reduction and CMOS integration, etc. In this talk, I will present our recent progress on engineering the wafer-scale epitaxial MoS2 monolayer channel for back-gate and dual-gate scaled transistors.

Bio: Dr. Yuanyuan Shi is a researcher (Marie Curie fellow) at IMEC, Belgium. She received her Ph.D. degree (with Excellent “Cum Laude” Honor and Extraordinary PhD prize) in Nanoscience from University of Barcelona in 2018. Her research interests focus on novel materials and new concepts/architectures based nanoelectronics, which target to bring new opportunities for the Post-Moore Era. Dr. Shi has published more than 60 research articles (including Nature Electronics, IEDM, ACS Nano, etc.), two book chapters and four international patents. She serves as an active committee member for IEEE EDS Nanotechnology committee and several IEEE flagship conferences, including IPFA, IRPS and EDTM. Dr. Shi also serves as a guest editor for Frontiers in Neuroscience and an active reviewer for Nature, Nature Electronics, Nature Materials, IEEE Electron Device Letters, and others. Dr. Shi is a recipient of 2020 Forbes 30 under 30 (Forbes), Marie Skłodowska-Curie Individual Fellowship (European Commission), 2020 Park AFM award (Park Systems), 2018 IEEE EDS PhD student fellowship (three winners globally each year), 2018 ADF-The Rising Stars Women in Engineering, etc.

Jayant Dsouza

Invited Talk Topic: Localization of Front-End Defects using Volume Scan Diagnosis

Advanced technology nodes with small feature sizes and increased design complexity have made identifying the root cause of yield loss increasingly time consuming. Scan-based diagnosis has been used to guide physical failure analysos and electrical failure analysis for a number of years. Front end of line (FEOL) defect mechanisms are especially predominant with advanced technology nodes. The use of cell-aware diagnosis combined with root cause deconvolution (RCD) machine learning can be leveraged to determine a root cause pareto for a population of failing dies. This pareto can also be used to improve the accuracy of the choice of die for physical failure analysis and localize the search area of front-end defects for failure analysis (FA).

Professor Christian Boit

Invited Talk Topic: Logic state imaging – From FA techniques for special applications to one of the most powerful hardware security side-channel threats

Bio: Prof. Christian Boit retired 2018 from Chair of Semiconductor Devices Department at Technische Universitaet Berlin, Germany. His research focuses on IC failure analysis (FA)  and contactless fault isolation (CFI). In recent years, he was also investigating hardware security risks introduced by CFI. Chris started at Siemens Semiconductors 1986 and participated 1990 -1993 in IBM / Siemens DRAM project East Fishkill, NY. Later, he was Director of FA at Infineon Technologies until taking the university position in 2002. Chris is an active supporter of the FA community. He was co-founder of EDFAS and General Chair of ISTFA 2002 and ESREF 2014.

Professor Massimo Vanzi

Invited Talk Topic: Wave aspects in Laser Diode Catastrophic Optical Damage

Bio: Massimo Vanzi is full professor at the University of Cagliari, Sardinia, Italy, working on Solid State devices, and in particular on device technology, Reliability, Failure Physics and Failure Analysis. The last two decades had a special focus on Photonics for telecom applications.
His activity lasts since 1980, with more than ten years spent in a private Italian telecom company, in charge of the physical microscopical analysis of a variety of electron devices, in tight cooperation with national public research centers. During this period, he also spent one year in Brasil on behalf of the International Telecommunication Union agency of the United Nations Organization, within a framework of support on telecom technologies.
Since 1992 he joined the University of Cagliari, and also entered first the Organizing Committee and then permanently the Steering Committee of the European Conference ESREF, that is the most important European symposium on electron device reliability.
In the last decade he cooperated with Huawei Technologies on several topics related to Reliability of advanced solid state devices, with an initial particular emphasis on Photonics.
His main contributions on Photonics range from modelling of laser diodes for linking physical phenomena (including degradation mechanisms) to external measurable quantities (failure modes) to protocols for practical measurements. Among them, the most recent achievement is a complete campaign for reorganizing gain measurement in several different kinds of laser diodes.”