Invited Speakers


Professor Tan Chuan Seng

Invited Talk Topic: 3D MIM Capacitor Embedded in TSV: Concept, Device Demonstration, Reliability and Applications

In this work, a novel integrated capacitor, called “3D MIM Capacitor Embedded in TSV” is proposed, designed, fabricated, and characterized for application in integrated circuits (ICs) with through-silicon vias (TSVs). A significant capacitance density enhancement can be achieved for this 3D embedded capacitor, because it leverages on the high aspect ratio structure of TSVs. Compared to conventional trench capacitor, this technology does not consume additional silicon area because it is embedded in the trenches of existing TSVs, instead of dedicated trenches. An ultrahigh capacitance density of 5,621.8 nF/mm2 was envisioned according to our model, which is ~13× of 440.0 nF/mm2 from a conventional trench capacitor with the same design parameters. A leakage current density as low as 1.61×10-7 A/cm2 at 4.3V and a breakdown voltage greater than 9.5 V were measured for a sample with a capacitance density of 3,776.6 nF/mm2. In addition, the reliability of the 3D MIM and potential new applications it enables are discussed.

Bio: Professor Chuan Seng Tan received his BEng degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his MEng degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In March 2014, he was promoted to the rank of Associate Professor (with tenure) and in September 2019, he was promoted to the rank of full professor. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology. He provides his service as committee member for International Conference on Wafer Bonding, IEEE-3DIC, IEEE-EPTC, IEEE-ECTC, IEEE-EDTM, IEEE-GFP and ECS-Wafer Bonding. He is an associate editor for Elsevier Microelectronics Journal (MEJ) and IEEE Transactions on Components, Packaging and Manufacturing Technology. He is a senior member of IEEE and a recipient of the 2019 Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS). Beginning in June 2019, he serves as a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019.

Professor Weidong Zhang

Invited Talk Topic: Reliability and Characterization of GeSe OTS Selector Device

Selector device with high on-state current, high half-bias nonlinearity and excellent endurance is critical to suppress the sneak path in high-density cross-point resistive switching memory arrays. Based on novel characterization and supported by first-principles simulations, filamentary-type switching, Weibull distribution of time-to-switch-on/-off and Vth relaxation in GexSe1-x OTS selector device are demonstrated and associated with defect delocalization/localization. Its endurance degradation and recovery mechanisms are identified as delocalized slow defects accumulation and Ge-Se segregation/crystallization. An optimal refreshing scheme is designed that can improve the endurance by more than five orders. This work provides new insights to the OTS switching, relaxation and degradation mechanisms and guidance for performance improvement.

Bio: Weidong Zhang is a professor of nano-electronics, leading the memory devices research at Liverpool John Moores University (LJMU), where the research in this field is ranked 11th and 26th in the last two UK government research assessments. He is the principal investigator and co-investigator of a number of research projects with a total value of more than £3 million, including five prestigious research grants from the Engineering and Physical Sciences Research Council (EPSRC), a leading UK government research funding council. He has led the LJMU’s collaboration with IMEC memory device group for the past 14 years, whose partners include Intel, Micron, Samsung, western Digital, SK Hynix and Toshiba. His current research interests include characterization and quality assessment of resistive switching and flash memory and selector devices, CMOS devices based on Si, Ge and III-V materials, and GaN HEMT devices. His work is predominantly published in international journals and premier conferences, including Applied Physics Letters, IEEE Electron Device Letters, IEEE Transactions on Electron Devices. He has co-authored 10 papers in the flagship IEEE International Electron Device Meeting (IEDM) and 7 papers in IEEE Symposium on VLSI Technology (VLSI) in the past 10 years.

Professor Xing Wu

Invited Talk Topic: ESD failure analysis by using transmission electron microscopy at the atomic scale

Transmission electron microscopy (TEM), with its high spatial resolution and versatile external fields, is undoubtedly a powerful tool for the static characterization and dynamic manipulation of nanomaterials and nanodevices at the atomic scale. The rapid development of thin-film and precision microelectromechanical systems (MEMS) techniques allows the microstructure during ESD to be probed and engineered inside TEM under external stimuli such as electrical and thermal fields at the nanoscale. Here, taking advantage of advanced in situ transmission electron microscopy, we manipulated interfaces of ESD. The progress of the in situ TEM paves the way to future nanodevices.

Bio: Prof. Xing Wu received her bachelor’s degree in Electronic Engineering from Xi’an Jiaotong University (XJTU) China in 2008 and her PhD degree from Nanyang Technological University (NTU) Singapore in 2012 (supervisor: Prof. Kinleong Pey). Then, she worked at the Singapore University of Design and Technology (SUTD) and Southeast University (SEU). She is currently a professor at East China Normal University (ECNU) China. She has published more than 90 SCI journal papers including Nature Communications, Advanced Materials, and IEEE TED with more than 3000 citations. She holds more than 30 patents.