Dr. Julien Ryckaert

Compute scaling beyond the finFET era: the road to CMOS 2.0

imec, Belgium

While entering the nanosheet era, the semiconductor industry realizes that we’re not on a smooth scaling curve for scaling CMOS.

DTCO has been instrumental in leveraging the full capabilities of scaled devices since the early finFET days. Moving forward, many disruptions are expected in CMOS platforms to provide scaled competitive nodes. New device architectures (e.g., nanosheet and forksheet FETs, CFET) BEOL scaling boosters, backside technology, 3D partitioning, and heterogeneous integration will all become instrumental in providing a future for the scaling roadmap. This trajectory will bring us deep into the CMOS 2.0 era.

Bio: Julien Ryckaert received the M.Sc. degree in electrical engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000 specializing in RF transceivers, ultra-low power circuit techniques and analog-to-digital converters. In 2010, he joined the process technology division in charge of design enablement for 3DIC technology. Since 2013, he is in charge of imec’s design- technology co-optimization (DTCO) platform for advanced CMOS technology nodes. In 2018, he became program director focusing on scaling beyond the 3nm technology node as well as the 3D scaling extensions of CMOS. Today, he is vice president logic in charge of compute scaling.