Dr. Yeo Yee-Chia

Enabling Next-Generation Heterogeneously Integrated Computing Systems Incorporating Photonics

Agency for Science, Technology, and Research (A*STAR), Singapore

The application space of silicon photonics is increasingly broadened beyond high-speed transceivers for datacenter and telecommunications and into computing. In-package optical I/O will allow computing architectures to meet the demands of artificial intelligence and high-performance computing workloads.

In order to meet such demand with extremely high date rate optical interconnection, various materials such as III-V, lithium niobate, and barium titanate need to be integrated on silicon platform for enhanced photonic functions and device performances.  What are the tools, materials and processes challenges and opportunities associated with photonics heterogeneous integration? How can the supply chain prepare for this revolution?  We will also discuss the bottlenecks for technology development, including defect characterization, yield improvement, and machine learning for early failure prediction.  We will discuss how the gaps in semiconductor R&D will be addressed via an industry-ready, shared infrastructure for translational research, prototyping, and high-mix low-volume manufacturing.

Bio: Yee-Chia Yeo is an Assistant Chief Executive of the Agency for Science, Technology, and Research (A*STAR) and a Professor of Electrical and Computer Engineering at the National University of Singapore (NUS). He received his Ph.D and M.S. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, and the M.Eng and B.Eng degrees in Electrical Engineering from NUS. His expertise is in transistor architecture, device modelling and simulation, materials, tools and processing technologies. He published 680 research papers and is an inventor of 270 U.S. patents. He trained 44 PhD students. He spent 10 years at Taiwan Semiconductor Manufacturing Company (TSMC). He was Director of Research and Development (R&D) at TSMC where he led organisations spanning research, pathfinding, and development. He co-developed TSMC’s industry-leading 7 nm, 5 nm, and 3 nm technologies.